0. old reports waiting for ACK =============================================

1. Upcoming release ====================================================
- BUG: bug_files/hier1.rs: there are two C1's in the abstract model; figure what should happen when there's a ./ instantiation on a root sheet [report: aron]
- BUG: rendering bug bug_files/mirror/ [report: aron]
- BUG: new sheet, place stock diode symbol, right click, move to loclib -> devmap link breaks, error msg on compilation [report: barjac]
- BUG: bug_files/miloh-font.txt - font handle remains invalid after placing text and changing font with {e s} to "wire" [report: miloh]
- BUG: bug_files/aronh1/ export to tedax netlist [report=aron]
	- the true name of the nets are VBAT1 and VBAT2 (due to the rails on the root sheet)
	- the abstract model shows real name on the left side but ./ short name on the right side for name attr
	- netlist output goes with name attribute
	-> causes the two nets implicitly merged on the netlist
	-> name attribute should be either true name (VBAT1) or at least hierarchic name (B1/VBAT)
- BUG: open bug_files erichVK5-Tracking-PS-Metering.rs; using cursor click and drag 128k,92k end of wire and move this end to 56k,92k ; using cursor, click and drag now shortened horizontal 5V wire at about 42k,92k and drag downwards until y=76k; crash ensues [report: Erich]
- BUG: open bug_files/loop_sbb.rs, select all (e.g. {s a a}) and {s b b}) ->assert/crash [report: sebastienL7]
- FEATURE: extobj syms and chart drawing [report: Vuokko]
	- doc: mention how converting refdes to block won't do what's expected
	- doc: how to disband an extobj (break up group or remove extobj attrib)
- sim GUI [report: aron]
	- FEATURE: add "Duplicate" button in "test bench & mods cfg" and "output config" menus, it would be easier to experiment
	- FEATURE: disable items in "test bench & mods cfg", also useful for experiments
	- FEATURE: would be nice if items in "output config" can be renamed
	- BUG: every simulation (pressing the "run" button) leaves a directory in /tmp/ (with "plot_cache" in it)
	- FEATURE: in "run & output" tab, it would be nice to have a checkbox to hide numbers from the graph
- BUG: funcmap:
	- preview of large funcmap text; should probably have a scrollbar [report: Vuokko]
	- when the file has a typo in a key (e.g. waek_group, throw a warning instead of just ignoring the key [report: Vuokko]

2. Later releases ==========================================================
- librnd 4.5: look for TODO("librnd4.5:...")
- librnd 4.3: look for TODO("librnd4.3:...")
- librnd4.1 API upgrade:
	- lib_plot/plot_preview.c: LIBRND41 TODOs: e->coord_per_pix is available
		-> see bug_files/TODO/sim.patch
- FEATURE: font2:
	- check calls to rnd_font_fix_v1(); don't call it if ->height is loaded; maybe not needed at all with font2, multiline is handled in librnd
	- baseline: probably a bad idea, skip it (incompatible with multiline and bbox placement, adds a random offset for term lables)
- CLEANUP/BUG: memleak test: bug_files/2k.rs.xz; start with the file in GUI, then revert -> memleak (doesn't leak much with batch)
- BUG: csch_grp_ref_embed(), used in sym loclib paste and right click symbol context menu toref (to loclib) conversion is not undoable [report: Igor2]
- BUG: when creating a new project from menu, if the file name is edited from project.lht to anything else, throw a warning [report: Erich]
- needs librnd 5.0.0 API upgrade:
	- library window "Use selected" should have a tooltip on what exactly it does (for devmap: returns name only, does not update loclib); API: close buttons can't have tooltips [report: aron]
- file format version bump cschem-sheet-v2:
	- FEATURE: implement attribute symlinks (see design doc)
		- CLEANUP: attrib code decides if an attrib is a string or array by looking at string value != NULL
			- replace this with a type enum that has str, symlink and array
			- put string value and array into an union
			- the file format needs to save an extra bit if it's a symlink
		- create hierarchic examples (parameter passdown is already implemented: cschem/param/ in the sheet ref symbol)
		- BUG: altium had a =Device or =Footprint attribute somewhere, that should be a symlink [report: aron]
	- a connection object should have x;y displacement for the graphical object to be useful (or is it a grp_ref?); at the moment we are not drawing it at all
	- text flag for &entity;
		- implement new text flag/attr for &entity; (similar to dyntext)

3. NLnet ==========================================================
- extensions:
	- attrib symlinks (see above for file format v2)
	- multiline font: switch over to librnd multiline/alignment rendering
		- implement the halign property (watch out for x mirror: start is always toward the origin)
		- {e T} for multiline edit of single line text; {e t} should also do this if text has \n's
		- propedit should get a button for invoking the same {e T} popup
		- maybe cache whether text is multiline in an unsaved struct field
		- FEATURE: text vertical alignment (add in design doc and code); same rules as in halign [report: Ade]
	- bxl symbols
		- devmap is probably impossible as slotted symbols are just drawn multiple times, once per slot
		- needs API for multiple symbols from a single file (see pcb-rnd bxl footprint load)
	- eagle xml schematics
	- eagle xml libraries (lbr)
	- high level sim:
		- sim-to-spice compilation:
			- autodetect net type from pin types
			- auto-bridge as needed for mixed mode digital+analog
			- DOC: port type attributes (e.g. analog, ttl), also consider DRC, check coraleda std 2
			- lib_sim: elect network type (default is analog)
			- API? set port attributes for bridges where needed
		- BUG: stance is set temporarily using sch_sim_set_test_bench() for the compilation only but csch_stance_set() prints the permanent setting
		- BUG: womit_no_test_bench is not really implemented, see TODO#womit
	- netlist export formats: see TODO.netlist

4. Low prio ==========================================================
- FEATURE: DRC (requires query() on the abstract model):
	- noslot or rather uniq attribute (e.g. for resistors)
	- figure if fully overlapping ports (or symbols) can be or should be detected (see: two gnd symbols on top of eachother) [report: Erich]
	- it is easy to accidentally add a footprint to a terminal on a symbol instead of the symbol itself. This is not flagged on netlist export. Should it be harder to do this, or maybe a netlist exporter could indicate if footprints associated with terminals in symbols were not included in the export? [report: Erich]
	- accidentally adding a name to a rail exports a connection in the netlist with no associated component. Perhaps this would benefit from some sort of DRC check, like the "footprint attribute put on non-symbol" issue above. [report: Erich]
	- component pcb pinnum: check if pins are numbered from 1 (or 0) without discontinuities; could catch typos in footprint creation (example: Aron's orange pi zero usb pins on edakrill) [report: aron]
	- move drc/require_graphical_conn check from compiler to DRC, see TODO#rgc
	- DRC dialog in sch_dialogs
	- DRC menu and hotkey
- FEATURE: BoM template language: concat'd lists:
		- use case: v1.1 should have color and tolerance in the value
		- allow creating new attributes (or rather macros) using the same template
		- create one with: %escape.sym.a.color|% %escape.sym.a.value|% %escape.sym.a.tolerance|%
		- print it as %escape.macro|(unknown)% for the value column
- FEATURE: symbol meta layer drawing: draw lines from floaters back to their parent?
- FEATURE: check feasability: use non-graphical fawk sheet as calculator
	- e.g. voltage divider of R1 and R2 with input and output voltages specified, fawk calculates value for R1 and R2
	- how to query attributes of existing things?
	- how to guarantee the data sheet is compiled after the graphical sheets?
	-> probably better to have this in a "target script"
- BUG: enable multiport_net_merge, then bug_files/multiconn0.rs; move TP2 1k or 2k to the left; more than one connection is created because the vertical ports are overlapping and when the horizontal port is connected, but it figures connections only one by one so it doesn't dare to extend existing connections [report: Igor2]
- FEATURE: consider dangling wire end indication (see pool node)
- FEATURE: support for protel format? (.asc, differerent syntax and data model from io_altium) [report: Scott]
- TODO#38: rethink grp-ref-in-grp-ref with child xforms, maybe cache=1 is a bad idea
	- problem: ref1 -> ref2 -> grp -> text; ref2 is floater; if whole ref2 is rotated, we won't update anything in ref1's central xform list
- BUG: wirenet in group should work: load symnet.rs. select terminal and adjacent vertical line using negative selection box; convert selection to symbol. connect test point 1 to wire net. export netlist. do not assume wirenet is directly under the &direct in the tree [report: Erich]
- BUG: back annotation: abstract model: abstract model UUIDs are not implemented, annotation doesn't use them; either figure persistent uuids or use CMRs [report: Igor2]
- BUG: rewrite get_prjname() in dytext render
	- figure the path of the project file
	- project name change runtime (save-as); inalidate text objects (->rtext = NULL using csch_text_dyntext_inval()) to re-render the new name
- OPTIMIZE: do not re-create views multiple times in sch_rnd_prj_conf2prj(): start 'sch-rnd A.rs B.rs' from the same dir [report: Igor2]
- CLEANUP: code dups with pcb-rnd, consider moving some code to src_3rd/rnd_inclib:
	- query
	- undodialog
	- rename csch_ symbols to sch_rnd_ in plugins/
	- act_read
	- propedit; plan to move accessors into core in pcb-rnd first:
		- move query's fields sphash to core
		- write per object read accessor API that gets an sphash key "path", similar to query and returns a type:val or type:*val
		- write a string based API around this
		- replace query code then propedit map code
		- write a per object write accessor API using the same sphash ket "path" and type:val payload, maybe undoable flag
		- replace propedit set code
		- maybe expose this in lib_vfs/ vfs_access_obj()
- librnd4.0.0:
	- remove the whole project loading plug io: project files will be handled by librnd
	- once multi is moved over:
		- extend oidpath to generate and accept sheet prefix with $uuid/
		- act_draw should be able to use it as scope
		- act_draw should be able to return oidpath with $uuid/
		- query() should be able to return/convert lists like that for scripting

6. TODO() tags ==========================================================
	- bitmap:     needed for bitmap objects
	- fungw:      may need fungw API change
	- multi:      multiple sheet support
	- hierarchic: needed for hierarchic projects
